Cadence’s latest news comes in the form of its PHY and controller IP for PCIe 6.0 passing official PCI-SIG compliance testing on the very first attempt.
PCIe is the backbone connecting accelerator cards, network interfaces, and storage devices inside AI data centers, and getting a new generation of the standard through compliance testing cleanly is a strong signal that the technology is actually ready for mass production.
By working closely with PCI-SIG, test equipment makers, and other industry partners well ahead of the formal workshop, they are able to run interoperability tests to catch and fix issues before the official evaluation even happens. And with that being done, Positron AI has licensed Cadence’s SerDes IP for PCIe 6.0 for its AI inference accelerator chip.
On the technical side, Cadence’s PCIe 6.0 solution includes a complete PHY and controller built in silicon, ADC- and DSP-based equalization, firmware-optimized SerDes operation, and multi-protocol flexibility, all while staying optimized for low power. It’s currently certified for x8 configuration on TSMC’s N3 process, and Cadence says the full subsystem is available now for SoC providers looking to design it into their chips. The company’s PCIe portfolio actually extends further, too, with solutions already built out up to the PCIe 7.0 specification.
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