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To help simplify that process, Cadence has introduced the AuraStack AI Super Agent on Allegro AI Studio, a new agentic AI platform designed for printed circuit board (PCB) and advanced packaging design to help streamline the process of creating larger and more complex connections and support of advanced AI systems.

Cadence introduces AuraStack AI Super Agent to streamline PCB and packaging design 1

The platform brings AI-assisted planning, implementation and analysis into a single environment, helping engineers move from concept to manufacturing more efficiently. Built on the same AI architecture as Cadence’s ChipStack AI Super Agent, AuraStack utilizes multiple AI agents to automate different stages of the design workflow.

Accelerated by NVIDIA Blackwell GPUs and NVIDIA CUDA-X, it coordinates tasks across system planning, physical implementation and multi-physics analysis, reducing the need for manual iterations between engineering teams. As a result, the unified workflow is capable of continuously evaluating electrical, thermal, and mechanical processes altogether throughout development.

Engineers benefit from this in terms of monitoring factors such as signal integrity, power integrity, thermal performance, mechanical stress, vibration and fatigue earlier in the design cycle, making it easier to spot potential issues before they become expensive redesigns.

Cadence also says AuraStack creates a shared design environment that allows different engineering disciplines to collaborate using a single source of truth. This helps streamline constraint management, IP reuse, place and route, manufacturability checks and product optimization, while also supporting co-optimization with advanced packaging technologies.

According to the company, the AuraStack AI Super Agent can reduce time to market by up to 2x while increasing engineering productivity by as much as 15x. By combining AI-driven automation with Cadence’s simulation and signoff tools, the platform is designed to help teams deliver more reliable products with fewer late-stage design iterations.


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