JEDEC has published the specs for the new UFS 3.1 storage chip in an update for the new standard. This new standard brings speed and power efficiency improvement which will be beneficial for smartphones and other embedded uses.
Under the new UFS 3.1 standard, there’s a new optional companion chip too, called the UFS Host Performance Booster (HPB) Extension.
According to XDA Developers, there are three key improvements that are found in the new UFS 3.1 chip:
- Write Booster: a non-volatile SLC cache
- DeepSleep: new low-power state
- Performance Throttling Notification: notifies the host device that the performance is hindered due to high temperature
What I’m personally interested here is Write Booster. This is a hardware-enabled feature presumably speeds up the process of writing by acting as a buffer. It is in between the host and the NAND flash chip. The data will be quickly transferred to the SLC cache drive first before writing into the NAND flash chip.
However, since the high-speed cache will be relatively smaller in capacity than the storage itself, the high write speed will drop back to a lower speed if the SLC cache drive is full.
As for the Host Performance Booster (HPB) Extension, it creates and stores an address map of the UFS storage. This is exceptionally helpful for large capacity storage chips as the memory controller doesn’t need to search for where is writable or not.
As the years passed since the first UFS chip was made and used, it has come down in cost to the point where even budget smartphones are using UFS 2.1 storage chips. The older eMMC flash storage chips have been slowly going out of phase as UFS chips have come down in cost over the course of a few years. It’s amazing to see technology trickling down to become cheaper
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